The DDR memory controller is able to connect to devices under the conditions listed in Table: System Memories.
Table 17-1: DDR Memory Controller Conditions
Parameter |
Value |
Notes |
---|---|---|
Maximum total memory density (GB) |
34 |
This is the maximum supported density. |
Total data width (bits) |
16, 32, 64 |
16 and 64-bit LPDDR4 are not supported. 16-bit is supported for DDR4 only. |
Component memory density (Gb per die) |
0.5, 1, 2, 4, 6, 8, 12, 16 |
3, 6, 12 and 16Gb single-channel LPDDR4 are not supported. 6, 12, 24 and 32Gb dual-channel LPDDR4 are not supported. |
Component data width (bits) |
8, 16, 32 |
4-bit devices not supported. Byte-mode LPDDR4 devices not supported. |
Number of ranks |
2 |
|
Number of row address bits |
17(2) |
Limited by the memory controller. |
Number of bank address bits |
3 |
|
Bank group |
2 |
|
MEMC_FREQ_RATIO |
2 |
DDR PHY to controller clock ratio (2:1). |
Notes: 1.3DS DDR4 is not supported in PS. 2.LPDD4 support is limited to 16 row bits. DDR4 support is limited to 17 row bits. DDR3, DDR3L, and LPDDR3 are limited by their DRAM specifications. |
,
Table: Example Memory Configurations lists some memory configuration examples. The memory configuration speeds are listed in the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2].
Note: Table: Example Memory Configurations lists just some of the possible memory configurations. Other configurations are possible.