DDR PHY Features

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Complete PHY initialization, training, and control.

Automatic differential data strobe (DQS) gate training.

Delay line calibration and voltage threshold (VT) compensation.

Automatic write leveling.

Automatic read and write data bit deskew and eye centering.

Automatic address/command bit deskew and eye centering for LPDDR3.

Automatic bit deskew and eye centering for LPDDR4.

Enhanced power saving support.

PHY control and configuration registers.

Compatible with the DFI 4.0 PHY interface standard.