The six DDR PLLs provide fast, accurate clocking to the I/O buffers interfacing to the DRAMs. The DDR_REF_CLK provides the source clock to the PLLs, which are controlled by six sets of registers. The data and ECC registers can be updated individually or as a group using the broadcast set of registers, PLLCR{0:5}. The PLL control architecture is shown in This Figure.
The DDR controller PHY consists of the following units.