DDR PHY PLL Control

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The six DDR PLLs provide fast, accurate clocking to the I/O buffers interfacing to the DRAMs. The DDR_REF_CLK provides the source clock to the PLLs, which are controlled by six sets of registers. The data and ECC registers can be updated individually or as a group using the broadcast set of registers, PLLCR{0:5}. The PLL control architecture is shown in This Figure.

Figure 17-8:      DDR PHY PLL Control Architecture

X-Ref Target - Figure 17-8

X19906-ddr-control-architecture.jpg

The DDR controller PHY consists of the following units.