DDR QoS Control Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 17-31:      DDR QoS Control Registers

Register Name

Register Description

PORT_TYPE

Set port type register.

QOS_CTRL

Set port type register.

RD_HPR_THRSLD

Set value for read high-priority read (HPR) CAM threshold.

RD_LPR_THRSLD

Set value for read low-priority read (LPR) CAM threshold.

WR_THRSLD

Set value for write CAM threshold.

ZQCS_CTRL0

ZQCS control register 0.

ZQCS_CTRL1

ZQCS control register 1.

ZQCS_STATUS

ZQCS status register.

DDRC_EXT_REFRESH

DDRC external refresh control register.

DDRC_EXT_REFRESH_RANK0_REQ

DDRC_EXT_REFRESH_RANK1_REQ

QOS_IRQ_STATUS

Interrupt status register for intrN. This is a sticky register that holds the value of the interrupt until cleared with a value of 1.

QOS_IRQ_MASK

Interrupt mask register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.

QOS_IRQ_ENABLE

Interrupt enable register. A write of zero to this location unmasks the interrupt. (IMR: 0)

QOS_IRQ_DISABLE

Interrupt disable register. A write of one to this location masks the interrupt. (IMR: 1)

DDRC_URGENT

DDRC urgent sideband signal control register.

DDRC_QVN_CTRL

DDRC QVN control register.

DDRC_MRR_STATUS

DDRC MRR register status.

DDRC_MRR_DATA{0:11}

DDRC MRR register data {0:11}.

DDR_CLK_CTRL

DDR subsystem clock control.