DDR QoS Controller

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DDR memory controller implements the top-level QoS policy for the six ports it supports for DDR access. The QoS is a priority based scheme, where each master in a system can assign a priority value to a transaction request where a servicing node with a choice of more than one transaction selects the transaction with the higher QoS value to process first. The system-level QoS implements two major objectives: Prevention of Head-of-Line Blocking and Traffic Classes.