DDR Subsystem Overview

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DDR subsystem (This Figure) is divided into two major blocks, the DDR memory controller and the DDR PHY and I/O, and includes the DRAM memory device(s).

Figure 17-4:      DDR Subsystem Block Diagram

X-Ref Target - Figure 17-4

X15350.jpg

The DDR memory controller consists of four major blocks: an AXI port interface, a port arbiter, a DDR controller, and the APB register block. The AXI port interface (XPI) interfaces the AXI application port to the memory controller. It converts AXI burst into read and write requests that are forwarded to the port arbiter. The port arbiter block arbitrates command requests from multiple AXI port interfaces and ensures maximum memory bus efficiency. The DDR controller (DDRC) block contains a logical content addressable memory (CAM) that holds information on the commands. The CAM is used by the scheduling algorithms to optimally schedule commands to be sent to the PHY, based on priority, bank/rank status and DDR timing constraints.