DLL Clock Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DLL input frequency to the SD controller comes from the PLL output of the IOPLL or RPLL (not from the VCO output). The SD controller DLL input frequency can be changed by the IOPLL or RPLL in the CRL_APB.DLL_REF_CTRL register. The DLL mode is automatically selected by the SD controller when the SD output clock frequency is more than 25 MHz; however, the minimum DLL clock frequency is 33 MHz. The DLL mode supported SD reference clocks are 50 MHz, 100 MHz, and 200 MHz. The reference clock values are updated in the IOU_SLCR.SD_CONFIG_REG1 base clock. In the DLL mode of operation, the tap delays in the IOU_SLCR.{SD_ITAPDLY and OTAPDLY} registers must be programmed.

The input tap delay programming sequence is as follows using the IOU_SLCR register set.

1.A DLL reset is issued.

2.The sdx_itapchgwin is set (to gate any glitches on the line).

3.The sd0_itapdlyena is enabled and the tap delay values are programmed.

4.The sdx_itapchgwin is cleared after setting the input tap delay.

5.The DLL reset is released. Wait for the DLL to lock.

The output tap delay programming sequence is as follows:

1.A DLL reset is issued.

2.The tap values are programmed.

3.The DLL reset is released. Wait for the DLL to lock.

Note:   Refer to the programming sequence in the SD Change Bus Speed section for the DLL reference clock setting.