DMA

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The controller for PCIe contains a high-performance 4-channel direct memory access (DMA) engine. Each channel can be programmed for either transmit or receive DMA operation. Each channel can be controlled from both the PCIe or AXI domains. The DMA supports separate source and destination scatter-gather queues. The DMA hardware is responsible for merging the source and destination information for data movement. The scatter-gather elements can be located in either PCIe or AXI memory.

Each DMA channel implements 128 bytes of DMA registers. DMA channel registers are accessed through AXI slave when AXI transaction hits the DMA register translation. The channel registers are at (DREG + 0x0) for first channel, (DREG + 0x80) for second channel and so on. DMA channel registers are accessed through PCI Express through the BAR associated with DMA channel registers (cfg_dma_reg_bar). This access is by default BAR0. DMA channel registers are at (BAR0 + 0x00) for the first channel and (BAR0 + 0x80) for the second channel and so on.

Table 30-6:      DMA Channel Address Map

DMA Channel

AXI Address

PCIe Address

0

DREG_BASE

cfg_dma_reg_bar(1)

1

DREG_BASE + 0x80

cfg_dma_reg_bar + 0x80

2

DREG_BASE + 0x100

cfg_dma_reg_bar + 0x100

3

DREG_BASE + 0x180

cfg_dma_reg_bar + 0x180

Notes:

1.By default, cfg_dma_reg_bar is BAR0.