DMA–AXI Master

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DMA unit generates AXI requests for the RXFIFO. It is a master on the AXI interface. The DMA module uses the AXI write channel to initiate AXI write requests that write RXFIFO data into the external memory (for example, DDR). This 32-bit AXI master interface allows access to the PS slaves via the top-level interconnect. An APB interface is provided for control and monitoring of the DMA write-channel module's functions. There is a single interrupt output that is sent to the DMA logic where it is combined with other controller interrupt sources to become a single system interrupt. The DMA controller does not support unaligned data transfers. All the data transfers are word aligned.

The DMA memory transactions will be routed to the CCI.