DMA Channel Control and Status Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

There are four DMA channels at offsets 0x00 for channel-0, 0x80 for channel-1, 0x100 for channel-2, and 0x180 for channel-3. Each channel has its own control and status register set (Table: DMA Channel Control and Status Registers).

Table 30-14:      DMA Channel Control and Status Registers

Register Name

Description

DMA_CHANNEL_SRC_Q_PTR_LO

Source queue base address Low.

DMA_CHANNEL_SRC_Q_PTR_HI

Source queue base address High.

DMA_CHANNEL_SRC_Q_SIZE

Source queue size.

DMA_CHANNEL_SRC_Q_LIMIT

Source queue limit pointer.

DMA_CHANNEL_DST_Q_PTR_LO

Destination queue base address Low.

DMA_CHANNEL_DST_Q_PTR_HI

Destination queue base address High.

DMA_CHANNEL_DST_Q_SIZE

Destination queue size.

DMA_CHANNEL_DST_Q_LIMIT

Destination queue limit pointer.

DMA_CHANNEL_STAS_Q_PTR_LO

Source status queue base address Low.

DMA_CHANNEL_STAS_Q_PTR_HI

Source status queue base address High.

DMA_CHANNEL_STAS_Q_SIZE

Source status queue size.

DMA_CHANNEL_STAS_Q_LIMIT

Source status queue limit pointer.

DMA_CHANNEL_STAD_Q_PTR_LO

Destination status queue base address Low.

DMA_CHANNEL_STAD_Q_PTR_HI

Destination status queue base address High.

DMA_CHANNEL_STAD_Q_SIZE

Destination status queue size.

DMA_CHANNEL_STAD_Q_LIMIT

Destination status queue limit pointer.

DMA_CHANNEL_SRC_Q_NEXT

Source queue next pointer.

DMA_CHANNEL_DST_Q_NEXT

Destination queue next pointer.

DMA_CHANNEL_STAS_Q_NEXT

Source status queue next pointer.

DMA_CHANNEL_STAD_Q_NEXT

Destination status write only to initialize the DMA channel.

DMA_CHANNEL_SCRATCH0

Scratchpad register.

DMA_CHANNEL_SCRATCH1

Scratchpad register.

DMA_CHANNEL_SCRATCH2

Scratchpad register.

DMA_CHANNEL_SCRATCH3

Scratchpad register.

DMA_CHANNEL_PCIE_INTERRUPT_CONTROL

PCI Express interrupt control.

DMA_CHANNEL_PCIE_INTERRUPT_STATUS

PCI Express interrupt status.

DMA_CHANNEL_AXI_INTERRUPT_CONTROL

PCI Express interrupt control.

DMA_CHANNEL_AXI_INTERRUPT_STATUS

AXI interrupt status.

DMA_CHANNEL_PCIE_INTERRUPT_ASSERT

PCI Express interrupt assertion.

DMA_CHANNEL_AXI_INTERRUPT_ASSERT

AXI interrupt assertion.

DMA_CHANNEL_DMA_CONTROL

DMA channel control.

DMA_CHANNEL_DMA_STATUS

DMA channel status.