DMA Channel Flow Control

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Each DMA channel contains three internal per-channel first in, first out (FIFO) buffers.

1.One FIFO caches up to eight source SGL elements.

a.The buffer is filled by reading the source SGL queue, that is made available as the SRC_Q_LIMIT register is updated.

b.The buffer is emptied when DMA transactions, that fully satisfy the size of the current source SGL element, are created.

2.One FIFO caches up to eight destination SGL elements.

a.The buffer is filled by reading the destination SGL queue that is made available as the DST_Q_LIMIT register is updated.

b.The buffer is emptied when DMA transactions, that fully satisfy the size of the current destination SGL element, are created.

3.One FIFO caches up to four DMA completion status.

a.The buffer is filled when DMA transfers with SRC SGL EOP == 1 completes.

b.The buffer is emptied when DMA completion status is written to the DMA completion status (STAS/SATD) queues.

DMA channels arbitrate amongst other DMA channels and bridge functions, using a round-robin arbitration scheme, to carry out a DMA transfer. The DMA transaction size arbitrated is up to 512 bytes for x1 to x4 PCI express lanes.

The source SGL element, and the destination SGL element are available in the internal FIFO cache. The DMA completion status FIFO has at least one element available to receive DMA completion status. When a DMA source SGL with EOP == 1 completes, the DMA completion status is written into the per channel DMA completion status internal FIFO until it can be written to the external STAS/STAD DMA completion status queues.