DMA Controller Functional Description

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The Zynq UltraScale+ MPSoC DMA (This Figure) is a general-purpose DMA for memory-to-memory, memory-to-I/O, I/O-to-memory, and I/O-to-I/O transfers.

Figure 19-1:      DMA Block Diagram

X-Ref Target - Figure 19-1

X15366-dma-block.jpg

The DMA acts as an AXI-4 master. Each channel can be independently enabled or disabled at any time. DMA supports pause functionality per-channel, which allows software to pause the channel using a descriptor and allows software to program new sets of descriptors. Software can resume the channel once it has programmed a new set of descriptors.

The DMA implements a common buffer that is sized to allow the DMA to utilize the full AXI bandwidth available. All channels share the common buffer. A common structure is automatically managed where software enables and disables the channel without concern for the allocation of buffer per channel. Each channel uses the available buffer on a first come first serve basis. Buffer utilization of each channel can be controlled by programming issuing capability of each channel and rate control. DMA supports two modes of operation, simple register-based DMA or scatter-gather DMA.

The DMA implements independent SRC and DST descriptors that can transfer any size payload (up to 1 GB). Descriptor payloads can start and end at any alignment. For some AXI slaves, overfetch of data is not allowed on the read channel. For these slaves, software can disable overfetch. Software can independently enable/disable overfetch on each DMA channel. Over-fetch disable can significantly impact DMA efficiency (depends on payload alignment). Xilinx advises only using this feature if it is required by an AXI slave.