DMA Error Handling

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DMA core associates the DMA errors with the source DMA channel and reports the errors on a per DMA channel basis.

When any DMA error occurs (as listed in DMA Error Detection), it is handled by the DMA channel as follows.

1.DMA enable register value is set to 0 (if 1).

°No new DMA operations are scheduled.

°DMA operations, started while the DMA was still enabled, continue for completion.

Note:   After the error is detected, expect continued DMA activity for a short period of time for the already in process transactions to complete.

2.PCIe DMA error and AXI DMA error registers are set to 1 to log the error.

3.A PCIe and AXI interrupt event is scheduled and reflected in the PCIe interrupt status and AXI interrupt status. Error interrupts are handled the same way as regular DMA interrupts.

°The same interrupt vector is used as for regular DMA completion interrupts.

°The interrupt is generated only when interrupts are enabled. Software can read the PCIe DMA error and/or the AXI DMA error to determine if the interrupt is generated due to an error.

When a DMA transaction fully completes, and (normally) a status queue element is written, then any errors detected during the DMA are reported in the status queue element written during DMA completion. This is a common scenario for small DMA operations. For larger DMA, because DMA operations are halted as soon as possible after detecting a DMA error, the DMA transaction with the error does not complete and the status queue element is not written.

When an error occurs, the software can continue operation without performing a system reset (depending on the severity of the error). In such cases, the DMA channel must be reset before reusing it again. For more details on how to reset a channel, refer to the Programming Topics.