DMA Mode Configuration Sequence

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.DMA configuration

°Program the QSPIDMA_DST_ADDR with the destination location (word aligned).

°For memories greater than 32 address bits, the QSPIDMA_DST_ADDR_MSB must be configured.

°Program the QSPIDMA_DST_SIZE with the number of words to transfer (word aligned).

°Program the QSPIDMA_DST_CTRL and QSPIDMA_DST_CTRL2 as required.

2.Quad-SPI I/O mode configuration

°Configure the MODE_EN bits to 2'b10 in the GQSPI_CFG register.

°Program the generic FIFO for writing the command, flash memory address, dummy cycles, and transfer size.

In all the modes listed, one or two SPI memories can be used, but the lower memory should always be present in dual-parallel mode. Configure the two memory devices to use separate data buses to double both throughput and storage size or a common shared data bus to reduce pin count with double storage size.

By default, the Quad-SPI memory subsystem comes up in I/O mode to allow users to configure the flash memory or to carry out different type of memory operations.