DMA Packet Buffer

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DMA uses packet buffers for both transmit and receive paths. This mode allows multiple packets to be buffered in both transmit and receive directions. This allows the DMA to withstand far greater access latencies on the AXI and make more efficient use of the AXI bandwidth.

Full packets are buffered, which allows the following.

Discard packets with error on the receive path before they are partially written out of the DMA. This saves AXI bus bandwidth and driver processing overhead.

Retry collided transmit frames from the buffer. This saves AXI bus bandwidth.

Process the transmit IP/TCP/UDP checksum generation offload.

With the packet buffers included, the structure of the controller datapaths is as shown in This Figure.

Figure 34-8:      DMA Packet Buffer

X-Ref Target - Figure 34-8

X15515-dma-packet-buffer-block.jpg

In the transmit direction, the DMA continues to fetch packet data up to a limit of 2048 packets, or until the buffer is full. The size of the buffer has a maximum usable size of 32 KB.

In the receive direction, if the buffer becomes full, then an overflow occurs. An overflow also occurs if the limit of 2048 packets is breached. The size of the packet buffer has a maximum usable size of 32 KB.