DMA Performance Requirements

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DMA provides 100% efficiency in the following scenario.

Read and write descriptor payload are 128-bit aligned (in scatter-gather mode)

SRC and DST descriptors are 256-bit aligned

SRC and DST payload is >4 KB

100% efficiency is achieved when there is no back pressure on the read and write AXI channels and DMA fully utilizes AXI read and write channels.