DMA Programming Model for FCI

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DMA implements one FCI per channel. An FCI interface can be independently controlled per channel. After each DMA transaction is done, the DMA channel clears both the channel EN and FCI_EN flags. Software must enable the FCI interface for each DMA transaction. If the FCI interface is not enabled (FCI_EN = 0), the DMA channel flushes all incoming credits.

Credits are only valid when the FCI interface is enabled (FCI_EN = 1).

Setup channel mode (simple and scatter gather mode).

ZDMA_CH_{DATA, DSCR}_ATTR attribute registers.

Setup DMA mode:

°Simple mode, program the DSCR registers.

°SG mode, program the DSCR in memory and program the DSCR start address register.

Set the FCI control parameters, ZDMA_CH_FCI [EN, SIDE].

Set the enable bit, CH2_CTRL [EN]. This provides a trigger to the DMA channel.

The DMA channel provides transaction acknowledgment for all valid credits received after the ZDMA_CH_FCI [EN] bit is set. The DMA channel clears ZDMA_CH_FCI [EN] once it is done with the DMA transaction. The software must enable FCI along with the channel enable for subsequent DMA transfers.

The suggested use-model for your applications follows.

SRC and DST payload addresses are aligned to programmed AXI burst length and an over fetch is enabled.

Software provides the transfer size details to the flow control slave.