DMA Read Transfer

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

On receiving the response end bit from the card for the write command (data flowing from host to card), the SD host controller acts as the master and requests the system/host bus. After receiving the grant, the host controller starts reading a block of data from the system memory and fills the first FIFO. Whenever a block of data is ready, the transmitter starts sending the data in the SD bus.

While transmitting the data in the SD bus, the host controller requests the bus to fill the second block in the second FIFO. Ping-pong FIFOs are used to increase the throughput. Similarly, the host controller reads a block of data from the system memory whenever a FIFO is empty. This continues until all the blocks are read from the system memory. The transfer complete interrupt is only set after transferring all the blocks of data to the card.