DMA Write Transfer

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The block of data received from the card (data flowing from card to host) is stored in the first half of the FIFO. Whenever a block of data is ready, the SD host controller acts as the master and requests the system/host bus. After receiving the grant, the host controller starts writing a block of data into the system memory from the first FIFO. While transmitting the data into system memory, the host controller receives the second block of data and stores it in the second FIFO. Similarly, the host controller writes a block of data into the system memory whenever data is ready. This continues until all the blocks are transferred to the system memory. The transfer complete interrupt is only set after transferring all the blocks of data to the system memory.

 

TIP:   The host controller receives a block of data from the card only when it has room to store a block of data in a FIFO. When both the FIFOs are full, the host controller stops the data coming from the card through a read wait mechanism (if the card supports a read wait mechanism) or by stopping the clock.