DRAM Initialization

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DDR PHY has an embedded state machines that performs DRAM initialization based on the DRAM type programmed into the PHY registers.

To trigger DRAM initialization using the PHY the PIR = x0000_0081 or PIR = x0010_0081 when RDIMM is required. Alternatively, you can have the DDR controller perform DRAM initialization. To do this, the PIR must be programmed with PIR = 0004_0001 to transfer control of the DFI interface from the PUB to the DDR controller.