As bit rates increase to 2133 Mb/s and beyond, maintaining timing margins in the DDR interfaces becomes more difficult. The PHY solution includes delay lines to compensate for per-bit skew due to factors such as PHY to I/O routing skews, package skews, and PCB skew.
The PHY contains automatic training sequences to perform read and write deskew, which align the data bits to the DQ bit with the longest delay using bit delay lines (BDL). After performing bit deskew, the read and write eye centering training is executed to place the strobe in the center of the eye defined by the bits in the respective byte.
During read or write eye training each individual byte lane has a register DXnGSR2 that contains error and warning status flags for each of the eye training algorithms.
Error conditions are fatal and the PHY will immediately terminate data training. Within the DXnGSR2 register, a bit field named ESTAT contains an error status code. This error status code identifies the sub-step where the failure occurred and the algorithm descriptions provide the conditions for the error and the associated error status code.
A warning status generally indicates that either the right or left edges of the data eye could not be detected. This can occur for a variety of reasons but this is more likely to occur during write bit deskew or write eye centering. When this warning occurs, the algorithm has assumed that the edge of the eye has been detected when it has exhausted the available DDL resources. This can result in a skewed center positioning of the DQS/DQS# within the data eye.
Read bit deskew, write bit deskew, read eye training, and write eye training are the data eye training steps.