Data Mask During ECC Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

When ECC is enabled, the memory controller generates a simple write to the DRAMs when the data is 64 bits wide and aligned to a 64-bit boundary. Otherwise, the controller performs a more time-consuming read-modify-write operation on the DRAM. In this case, the controller first fetches the read data from the DRAM and merges it with the write data from the AXI interconnect and generates the ECC bits. The controller then writes whole words with ECC to the DRAMs.

Note:   If a stream of partial writes are performed by an AXI port interface with high priority, it can have a major negative impact on the ability of other ports to access memory. For example, this can cause an isochronous video stream to drop data.