Data Training

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

After the PHY and SDRAM are successfully initialized, the PHY is trained for optimum operating timing margins. This includes CA training (LPDDR3 only), write leveling, the training of the DQS gating during reads, write latency adjustment, bit deskew, and the training of the read and write data eyes. Table: Data Training lists the various training options. This Figure through This Figure shows the flowcharts.

Table 17-35:      Data Training

CA training

This feature of the LPDDR3 memory is used for optimizing the setup and hold times of the CA bus relative to the memory clock.

Write leveling

This training is used to compensate for skew by aligning the clock with the data strobe at each SDRAM.

DQS gate training

This training executes a series of reads sweeping the read DQS gate over possible gating positions to discover an appropriate placement that results in successful read operations.

Write DQS2DQ training

LPDDR4 memory devices use an unmatched DQS-DQ path to enable high-speed performance and save power. As a result, the DQS strobe is trained to arrive at the DQ latch center-aligned with the data eye. The DQ receiver latches the data present on the DQ bus when DQS reaches the latch, and DQS2DQ training is accomplished by delaying the DQ signals relative to DQS such that the data eye arrives at the receiver latch centered on the DQS transition.

Write latency adjustment

This is second level of write leveling to find if extra pipeline stages need to be been added in the write path due to the write leveling and/or the board fly-by delays. After determining the write latency, a second sequence of writes and reads are issued to validate the computed latency adjustment setting.

Data eye training
(read, write)

This training is used at greater than 2133 Mb/s rates to compensate for per-bit skew due to factors such as PHY to I/O routing skews, package skews, PCB skew, etc. The PHY performs automatic training sequences for read and write deskew, which aligns the data bits to the DQ bit with the longest delay using a bit delay line (BDL). After performing bit deskew, the read and write eye centering training is executed to place the strobe in the center of the eye defined by the bits in the respective byte.

VREF training

Write and read eyes should be as wide as possible to provide a stable and robust memory access. The eye position depends upon LCDL, as well as VREF values. The write and read data eye training is used to find out the best eye position by changing LCDL values with an initial calculated and programmed VREF setting.

Figure 17-14:      Data Training Flowchart 1

X-Ref Target - Figure 17-14

X15361-data-training1-flowchart.jpg
Figure 17-15:      Data Training Flowchart 2

X-Ref Target - Figure 17-15

X15362-data-training2-flowchart.jpg
Figure 17-16:      Data Training Flowchart 3

X-Ref Target - Figure 17-16

X15363-data-training3-flowchart.jpg
Figure 17-17:      Data Training Flowchart 4

X-Ref Target - Figure 17-17

X15364-data-training4-flowchart.jpg