Data-side Memory System

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The data-cache unit (DCU) consists of the following sub-blocks.

The level 1 (L1) data-cache controller that generates the control signals for the associated embedded tag, data, and dirty RAMs, and arbitrates between the various sources requesting access to the memory resources. The data cache is 4-way set associative and uses a physically-indexed physically-tagged (PIPT) scheme for lookup that enables unambiguous address management in the system.

The load/store pipeline that interfaces with the DPU and main TLB.

The system controller that performs cache and TLB maintenance operations directly on the data cache and on the instruction cache through an interface with the IFU.

An interface to receive coherency requests from the snoop-control unit (SCU).