The CoreSight components provide the following capabilities.
•On-chip multicore debug including break point and single-step.
•For the APU MPCore, the embedded trace macrocell™ (ETM) is integrated into the MPCore and captures all CPU waypoints.
•For the RPU MPCore, the ETM captures CPU traces and is external to the MPCore.
•CoreSight system trace macrocell (STM) captures software driven trace and PL events.
•Cross-trigger interface (CTI) and cross-trigger matrix (CTM) allows cross triggering support among multiple trace-capture modules.
•Trace memory controller (TMC) with 8 KB ETF buffer captures and aggregates trace data from individual components. ETF can be used as a trace buffer, which software can read. It can also be used as a FIFO (to absorb bursts of trace traffic) for trace that is output into DDR or the trace-port interface unit (TPIU).
•TPIU is output to MIO or EMIO with double data rate and configurable width, with clock speed up to 125MHz.
•Arm CoreSight standard programming models for standard tool support.
•Standard bus interfaces for CoreSight compliant third-party cores.
°All trace capture modules are accessible from external JTAG interface via the Arm DAP controller or an AXI bus master.
°Low-power debug mode. JTAG, through the DAP, has direct memory-space accessibility without stopping the CPU low-power debug mode.
°Debug and trace visibility of the whole system.
°On-chip and off-chip buffers and storage for trace data.
°Time stamping to co-relate events.
°Single debugger connecting point for entire system debug.
•AMD debug components:
°Dump trace from selected AXI interconnect channels.
°Packetized trace for compatibility with Arm tools.
°General purpose signals to and from the PL.
°Trigger signals to and from the PL.