Deep-sleep Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The deep-sleep mode suspends the PS and waits to be woken up. The lowest power deep sleep is supported for wake sources GPI and RTC. Other sleep states are supported for wake sources of USB and Ethernet, with additional power for the wake source. Upon wake, the PS does not have to go through the boot process and the security state of the system is preserved. This reduces the restart time of the system.

The device consumes the lowest power during this mode while still maintaining its boot and security state. The PMU is placed in a sleep or suspend state waiting to be interrupted.

During the deep-sleep mode, the wake signal can be generated either through a GPI input routed from an MIO pin or by an RTC alarm.

Table: Deep-sleep Configuration summarizes the PS configuration in deep-sleep mode.

Table 6-14:      Deep-sleep Configuration

Configuration Type

Status

Description

Cortex-R5F

Powered down

 

TCM configuration

OCM configuration

Device security

In retention

In retention

Suspended

Either TCM or OCM is powered down.

Peripheral

Suspended

Wake up peripheral logic might be active.

PLLs

Powered down

 

System Monitor

Powered down

During power down, the SysOsc clock can go to 20 MHz ±50%.

RTC and BBRAM

Included

Switched to the VCC_PSAUX rail.

PMU

MPSoC debug

Suspended

Powered down

The wake logic is active.

MPSoC debug is mostly in FPD. The LPD portion is suspended.

eFUSE
Components outside the LPD

Suspended

Powered down

 

PL internal power

Powered down