After the PLLs have locked, the PHY executes delay line calibration before any further initialization task that uses a high-speed (controller) clock can commence.
Each master delay line has to be calibrated for the SDRAM clock period. This is done by measuring the number of delay line steps that are required to produce a delay equal to the DDR clock period. Each master delay line is calibrated independently. Delay line calibration is normally done as part of the PHY initialization sequence.
Once all delay lines have been calibrated, the calibration done status is asserted through a status register bit, PGSR0.DCDONE. The results of the calibration are available in the registers listed in Table: Master Delay Line Registers.
Table 17-12: Master Delay Line Registers
Register
|
Bits
|
Name
|
Description
|
Address
|
ACMDLR0
|
[8:0]
|
IPRD
|
Initial period: initial period measured by the master delay line calibration for AC.
|
0xFD0805A0
|
ACMDLR0
|
[24:16]
|
TPRD
|
Target period: target period measured by the master delay line calibration for AC. This changes with voltage and temperature.
|
0xFD0805A0
|
DX0MDLR0
|
[8:0]
|
IPRD
|
Initial period: initial period measured by the master delay line calibration for byte 0.
|
0xFD0807A0
|
DX0MDLR0
|
[24:16]
|
TPRD
|
Target period: target period measured by the master delay line calibration for byte 0. This changes with voltage and temperature.
|
0xFD0807A0
|
DX1MDLR0
|
[8:0]
|
IPRD
|
Initial period: initial period measured by the master delay line calibration for byte 1.
|
0xFD0808A0
|
DX1MDLR0
|
[24:16]
|
TPRD
|
Target period: target period measured by the master delay line calibration for byte 1. This changes with voltage and temperature.
|
0xFD0808A0
|
DX2MDLR0
|
[8:0]
|
IPRD
|
Initial period: initial period measured by the master delay line calibration for byte 2.
|
0xFD0809A0
|
DX2MDLR0
|
[24:16]
|
TPRD
|
Target period: target period measured by the master delay line calibration for byte 2. This changes with voltage and temperature.
|
0xFD0809A0
|
DX3MDLR0
|
[8:0]
|
IPRD
|
Initial period: initial period measured by the master delay line calibration for byte 3.
|
0xFD080AA0
|
DX3MDLR0
|
[24:16]
|
TPRD
|
Target period: target period measured by the master delay line calibration for byte 3. This changes with voltage and temperature.
|
0xFD080AA0
|
DX4MDLR0
|
[8:0]
|
IPRD
|
Initial period: initial period measured by the master delay line calibration for byte 4.
|
0xFD080BA0
|
DX4MDLR0
|
[24:16]
|
TPRD
|
Target period: target period measured by the master delay line calibration for byte 4. This changes with voltage and temperature.
|
0xFD080BA0
|
DX5MDLR0
|
[8:0]
|
IPRD
|
Initial period: initial period measured by the master delay line calibration for byte 5.
|
0xFD080CA0
|
DX5MDLR0
|
[24:16]
|
TPRD
|
Target period: target period measured by the master delay line calibration for byte 5. This changes with voltage and temperature.
|
0xFD080CA0
|
DX6MDLR0
|
[8:0]
|
IPRD
|
Initial period: initial period measured by the master delay line calibration for byte 6.
|
0xFD080DA0
|
DX6MDLR0
|
[24:16]
|
TPRD
|
Target period: target period measured by the master delay line calibration for byte 6. This changes with voltage and temperature.
|
0xFD080DA0
|
DX7MDLR0
|
[8:0]
|
IPRD
|
Initial period: initial period measured by the master delay line calibration for byte 7.
|
0xFD080EA0
|
DX7MDLR0
|
[24:16]
|
TPRD
|
Target period: target period measured by the master delay line calibration for byte 7. This changes with voltage and temperature.
|
0xFD080EA0
|
DX8MDLR0
|
[8:0]
|
IPRD
|
Initial period: initial period measured by the master delay line calibration for byte 8.
|
0xFD080FA0
|
DX8MDLR0
|
[24:16]
|
TPRD
|
Target period: target period measured by the master delay line calibration for byte 8. This changes with voltage and temperature.
|
0xFD080FA0
|