Description

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The SATA controller has the following primary interfaces.

The AXI slave interface is a 64-bit AXI slave interface with a 12-bit AXI ID and a 46-bit AXI address. This interface has a maximum burst length of one. A burst with a burst size more than one results in an AXI error. This restriction does not affect performance during normal operation.

The interrupt interface is used to signal interrupts to the host CPU. The interrupt controller has one bit assigned to the SATA block that is connected to the GIC. The interrupt signal routed to the GIC is a WIRE-OR output of the PORT0 interrupt, the PORT1 interrupt, and the command coalescing channel interrupt. In the interrupt separate mode, each interrupt output from PORT0, PORT1, and the command coalescing blocks are routed to the GIC. Refer to Table: APU Private Peripheral Interrupts for the interrupt ID of the SATA host controller block. Software must not enable the interrupt separation mode because it is not supported on the device.

The AXI master interface is used by the block to perform DMA operations for moving data between the host memory (example DDR) and SATA device (example hard drive). This interface has ability to initiate burst between 1 and 16 cycles. The master interface has 4-bit AXI ID buses that can take on one of four (programmable) ID values that are out of reset default to 0, 1, 2, and 3. The IDs are configured through the SATA_AHCI_VENDOR.PAXIC port register. The block can issue up to 16 read and write transactions through the AXI master interface. Out of reset, the maximum number of outstanding transactions (issuing ability) defaults to four reads and four writes, and it can be changed through the port AXI CFG register. This port only generates incremental bursts with lengths of 1, 4, 8, or 16 beats. The burst length is selected by the block based on FIFO fill levels and is not controllable by user. The AxCACHE bits can be controlled through the AXI cache control register. The AxPROT bits are controllable through the FPD_SLCR_SECURE register set as well as through the security (TrustZone) bus.

The SATA controller performs 8B/10B encoding and decoding functionality and uses 20-bit parallel interface to the PS-GTR block. The following sections describe each of the layers implemented as part of the SATA protocol stack.