Descriptor Setup

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The SRC and DST SGL elements need to be setup based on the required transfer flow.

For example, for the system to card transfers (host to AXI-CPU).

Setup appropriate flags in the SRC element on the host (buffer fetch direction PCIe and interrupt if required on the EOP element).

Setup appropriate flags in the DST element on the AXI-CPU (buffer write direction AXI and back-to-back packing of data if needed).

Setup appropriate flags for elements in a card-to-system (C2S) transfer.