The preferred process to disable an operational DMA channel (This Figure) is as follows.
1.Software stops adding new DMA transfers to the source and destination SGL queues. The last source and destination SGL queue elements given to the DMA channel to execute (via SRC/DST_Q_LIMIT registers) should be fully consumed by the final DMA transfer.
2.Software waits for all outstanding DMA operations to complete and processes the DMA completion status from the DMA completion status queue. Software implements a timeout in the event that the DMA operations are never complete. This can occur if software is not provided with the matching source and destination SGL elements that can be fully consumed.
3.Software writes DMA_Enable == 0 to the DMA channel. This disables the DMA channel.
4.Software reads the DMA_Running in the DMA channel. If DMA_Running == 0, then the DMA channel is finished with all the outstanding transactions. The software can optionally skip to step 6.
5.If DMA_Running == 1, then the DMA channel could not have finished all the outstanding transactions. One or more of its internal source SGL, destination SGL, or DMA completion status queues is not empty. Software writes DMA_Reset == 1, waits ³256 nS, and writes DMA_Reset == 0. Setting DMA_Reset == 1 flushes the internal DMA source SGL, destination SGL, and DMA completion status FIFOs.
You can use these steps when you use a single CPU mode, where a host driver manages the DMA channel. The driver on Arm will only be responsible for bridge initialization.