DisplayPort Clock Generators

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The video reference clock, dp_video_ref_clk, is based on the basic clock generator design with one divider and one clock enable as shown in This Figure. The input video clock is typically a 27 MHz base clock. The output clock frequency generated from the video clock generation block can typically be 27 MHz, 81 MHz, 135 MHz, or 270 MHz depending on the data rate or the fractional divide values of the PLL can be configured to generate the unique frequencies needed for the DisplayPort controller. The fractional mode of the PLL can be used to generate a specific video clock frequency.

Similarly, the audio reference clock, dp_audio_ref_clk, is generated using the basic clock generator design but, with two divisors and one clock enable.