The DisplayPort controller source system supports multiple video and audio channels which are used to get video/audio data from system DDR memory. These are known as non-live video/audio. To facilitate the data transfer from DDR to the DisplayPort controller, a DisplayPort DMA (DPDMA) block is included in the DisplayPort subsystem to handle six channels; three video channels, one graphics channel, and two audio channels. The DPDMA fetches the frame buffer data from the DDR and hands it over to the audio video buffer (AV buffer) inside the DisplayPort controller. The DPDMA uses an AXI stream interface with the DisplayPort controller, while it is connected to the DDR through the AXI interconnect in the PS. An AXI3 128-bit master interface is used by the DPDMA to connect with the PS interconnect.
Each DPDMA channel has a configuration register for the QoS value. By default, the input of the DisplayPort controller from the PL should have the QoS to set the video traffic class. Otherwise, small latency may choke the DMA and end up cutting the display. Refer to Zynq UltraScale+ Devices Register Reference (UG1087) [Ref 4].
The DPDMA supports the following features:
•Support for simultaneous read and write transactions.
•Six independent channels.
•Multiple outstanding transactions per channel.
•Fixed interval transaction scheduling.
•Simple memory buffer and 2-D buffer formats with line stride (for video).
•Memory-based descriptor task linked list with wrap option (a circular list of buffers).
•Support for autonomous operation with a circular task list.
•Each descriptor (per channel) provides programmable values to be programmed by system software.
•Support for line/buffer size that is not an integer multiple of the AXI burst size/length.
•Support for the option to set/clear buffer done flag in the descriptor.
•Support for the option to store a timestamp in the descriptor.
•Support for optional interrupt generation at the end of each task.
DPDMA does not support the following features:
•Varying burst length for each channel.
•A CRC option on the DPDMA.
•Redundant pixel formats for video and graphics.
This Figure shows the DPDMA block in the Zynq UltraScale+ MPSoC. The following section describes the descriptor structure of DPDMA.
The DPDMA block acts as an AXI master in the full-power domain (FPD) and has a 128-bit AXI master port. This block is primarily used for fetching descriptor data and descriptor updates. The DPDMA also implements the advanced peripheral bus (APB) port for register access. Upon a data fetch request from software, the DPDMA initiates read transfers from memory. This data is provided to the A/V buffer manager through the 128-bit data port.
The DPDMA block receives information regarding VSYNC, HSYNC, and active video time from the DisplayPort subsystem. On video channels, the DPDMA can read 256 bytes of data every burst (128 x 16) when the burst size is programmed as 16. The DisplayPort subsystem takes 32 pixel clocks to consume this data (4B/pixel video format). The DisplayPort requests data every 32 pixel clocks. The DPDMA block fetches 256 bytes of data on every AXI transaction and receives information regarding stride and line size from the descriptor field. Based on line start, line end, frame start, and frame end signals, the DPDMA reads the frame buffer from memory.
The DPDMA supports two descriptor payload formats, contiguous payload and fragmented payload. The contiguous payload format is efficient for bare-metal applications where large chunks of contiguous memory are available. On Linux systems, large chunks of contiguous memory allocation are difficult to obtain. To support display applications on Linux systems, the DPDMA implements a fragmented payload mode on the descriptor. It supports payload sizes as small as 4KB. The descriptor format is explained in more details in a later section.
The DPDMA uses a descriptor-based architecture. This allows software to divide frame buffers into data sets that are small as 4 KB. Software can maintain a circular chain of descriptors per channel. The DPDMA goes through the chain and provides data to the DisplayPort subsystem.
The DPDMA puts the following restrictions on size and alignment of the descriptor.
•Descriptor and data payload must start at a 256-byte aligned address.
°With this requirement, the DPDMA does not have to deal with a 4K crossing of an AXI burst.
°The DPDMA generates a fixed number of transactions every fetch request.
•The data payload must end at a line boundary or frame boundary.
°The payload cannot end within the line.
°This restriction is necessary for QoS to work efficiently. By doing this, the DPDMA ensures that it does not fetch a descriptor during active video time.
The DPDMA supports two descriptor formats to alleviate these restrictions.