Driver on a Zynq UltraScale+ MPSoC Endpoint

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Checks for PCIe link up before proceeding ahead with any other initialization.

2.Performs bridge initialization as described in Bridge Initialization.

3.Enables AXI interrupts by programming:

AXIPCIE_DMA0.DMA_CHANNEL_AXI_INTERRUPT_CONTROL[interrupt enable] = 1

AXIPCIE_MAIN.MSGF_DMA_MASK = 0x1

This example only uses the DMA channel 0 interrupt.

4.Wait for interrupt from host before setting up ingress translation aperture.

5.Once the interrupt (AXIPCIE_DMA0.DMA_CHANNEL_AXI_INTERRUPT_STATUS[software_int]) is received:

a.Read BAR2 or BAR4 via the ECAM aperture to obtain the BAR value host programmed in the Endpoint configuration space (BAR0 is dedicated to the bridge).

b.Setup the ingress source address to the BAR address and destination address to the desired destination address; program the ingress aperture size and enable the translation.

Note:   The handshake can also be implemented using a poll mode where the driver polls for a predefined signature value in the scratchpad registers of the DMA channel. Instead of reading the BAR address via ECAM and programming, the host system driver can pass the address and size via scratchpad registers. There are different ways of implementing this and one options is described. The memory enable bit in the command register in the PCIe configuration space can also be used to validate the BAR assignment.

6.Once translation is setup and to inform the host system, raise an interrupt to the host (AXIPCIE_DMA0.DMA_CHANNEL_PCIE_INTERRUPT_ASSERT[pcie_software_interrupt]) or write a signature value to the scratchpad register.