Dual-CPU Control

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DMA supports multi-CPU DMA operation, that is, each DMA channel can be managed by both host CPU as well as an AXI CPU.

The dataflow for this mode is described in this section. The example assumes that the Zynq UltraScale+ MPSoC’s integrated block for PCIe is an Endpoint.