Dynamic DDR Configuration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The controller is able to be configured for different memory settings at runtime while the DDR controller is in reset. Typically, this is used in DIMM topologies by reading the DRAM configuration from the DIMM SPD EEPROM via a I2C peripheral.

See Answer Record 75768 for more information.