Dynamic Mode and Baud Rate Change Limitations

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The generic Quad-SPI controller requires a reset (CRL_APB.RST_LPD_IOU2[qspi_reset]) to simultaneously switch both the baud-rate divisor and the dual-parallel mode. For example, when operating in the single or stacked mode and accessing the lower flash with a baud rate of 4 and switching to the dual-parallel or stacked dual-parallel mode with a baud rate of 2, a reset is required.