Dynamic - Refresh Related Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The refresh related registers are dynamic, however, to update them perform the following:

Change the refresh associated register as desired.

After the changed register is stable, toggle the RFSHCTL3.refresh_update_level signal.

The SDRAM controller recognizes the refresh_update_level signal change and updates all refresh-related register values accordingly. This mechanism is needed to avoid sampling errors in the target clock domain, as well as to allow the controller to provide special handling (such as issuing an additional refresh and resetting the refresh timer if needed) when a refresh-related timing register has changed.

The refresh related registers are dynamic, except RFSHCTL3.refresh_mode, which can only be programmed during the initialization or when the controller is in self-refresh mode. At initialization, the RFSHCTL3.refresh_mode must be set to match the refresh mode field of MR3, written to SDRAM via INIT4.emr3. When updating this register in self-refresh mode, the corresponding MR3 command is sent automatically after SRX. In this case, the INIT4.emr3 should be modified as well because the value written to the SDRAM via the MR3 command is taken from INIT4.emr3, and not from RFSHCTL3.refresh_mode.