The controller performs these steps when it detects correctable ECC errors:
1.Sends the corrected data to the PS core as part of the read data.
2.Writes the address, syndrome bits, and data mask bits to ECC registers in the DDRC register set.
3.Performs a RMW operation to correct the data present in the DRAM (only if ECC scrubbing is enabled (ECCCFG0.dis_scrub = 0). This RMW operation is invisible to the core. Only one scrub RMW command can be outstanding in the controller at any time. No scrub is performed on single-bit ECC errors that occur while the controller is processing another scrub RMW.
4.Sets the [DDRECC_CORERR] interrupt bit in the DDR_QOS_CTRL.QOS_IRQ_STATUS register.
The controller performs these steps when it detects uncorrectable ECC errors:
1.Sends the data with the error back to the AXI interconnect as the read data.
2.Writes the address and syndrome bits to ECC registers in the DDRC register set.
3.Generates an error response SLVERR on the AXI interface. If L2 cache is disabled, CPU receives the SLVERR response directly which can cause a Data Abort exception. If L2 cache is enabled, L2 cache reports the SLVERR by issuing an interrupt to CPU.
4.Sets the [DDRECC_UNCRERR] interrupt bit in the DDR_QOS_CTRL.QOS_IRQ_STATUS register.