ECC Poisoning

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Program DDRC.ECCCFG1 [data_poison_en] to 1'b1, which introduces the ECC errors on writes to the address specified by the DDRC.ECCPOISONADDR {0, 1} registers.

2.Selects the correctable data poisoning or uncorrectable data poisoning. Program DDRC.ECCCFG1 [data_poison_bit] bit (1'b0 - 2-bit (uncorrectable) data poisoning, 1'b0 - 1-bit (correctable) data poisoning).

3.Set the address to be poisoned in the DDRC.ECCPOISONADDR {0, 1} registers.

Note:   ECCPOISONADDR0[11:0], ecc_poison_col, must be burst aligned. In 64-bit bus width mode, ecc_poison_col[2:0] must be set to 0. In 32-bit bus width mode, ecc_poison_col[3:0] must be set to 0.

4.Write to the poison address. Subsequent reads to the same 1-2 DRAM burst length of addresses are detected.

A sample test program tests the ECC correctable/uncorrectable error detection by inserting error bits into DDR memory is described in the Zynq UltraScale+ MPSoC – 64-bit DDR Access with ECC technical article [Ref 25].