EMIO Signals

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section describes the operation of GPIO bank 3, bank 4, and bank 5. The register interface for the EMIO banks is the same as for the MIO banks. The EMIO interface differences are explained in this section.

The inputs come from the PL and are unrelated to the output values or the OEN (gpio.OEN_{0:5}) register. They can be read from the DATA_0_R0 register when their bit in the DIRM register is set to 0 (making it an input). The outputs are not 3-state capable and are not affected by the OEN register. The output value is programmed using the DATA, MASK_DATA_LSW, and MASK_DATA_MSW registers. DIRM must be set to 1 (making it an output). For more details on these registers, refer to Table: GPIO Register Overview.

Note:   Similar to MIO, there is no PL clock associated with the GPIO EMIO signals and should be considered asynchronous to PL logic.