EN_DSCR_DONE_INTR Field

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

If this bit is set, the DPDMA generates an interrupt to indicate that the processing of the current descriptor is complete. If the descriptor update is enabled, the DPDMA updates (writes back) the descriptor and waits for the BRESP (write response) to generate an interrupt. This ensures the coherency of the IRQ generation.

In case the DSCR update is not requested, it generates an interrupt after it receives all outstanding transaction responses, after the descriptor is processed.