Egress Endpoint Driver

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Checks for PCIe link up before proceeding ahead with any other initialization.

2.Performs bridge initialization as described in Bridge Initialization.

3.Enables AXI interrupts by programming:

AXIPCIE_DMA0.DMA_CHANNEL_AXI_INTERRUPT_CONTROL[interrupt enable] = 1

AXIPCIE_MAIN.MSGF_DMA_MASK = 0x1

This example only uses the DMA channel 0 interrupt.

4.Wait for interrupt from host before setting up ingress translation aperture.

5.Once the interrupt (AXIPCIE_DMA0.DMA_CHANNEL_AXI_INTERRUPT_STATUS[software_int]) is received:

a.Read the scratchpad to obtain the host system memory address allocated for egress transfers.

b.Setup the egress source address to AXI address (falling in the PCIe address domain) and destination address to the received host system memory address; program the egress aperture size and enable the translation.

Perform data transfers and signal the host system on completion to further process transferred by host system software.