Egress Transactions

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This Figure is a flowchart for egress transaction handling.

Figure 30-6:      Egress Transaction Handling

X-Ref Target - Figure 30-6

X15490-egress-pcie-transaction-handling-block.jpg

ECAM write and I/O write transactions are non-posted in the PCIe domain. Non-posted transactions must not be allowed to stall posted transactions to avoid deadlock conditions. These non-posted writes require arbitration for a PCIe tag and completion handling resources managed by the bridge's reorder queue. These non-posted writes are not queued in reorder queue and instead are queued into an additional non-posted write FIFO.