Egress Transfers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Egress refers to the AXI to PCIe direction. Typically, these transfers are achieved using the DMA however, egress transactions provide a way for an Endpoint to drive 4-byte transfers into the host system memory without using a DMA. This requires bus mastering to be enabled for the Endpoint. Additionally, egress translation aperture should be setup. For this, host system driver allocates memory and physical address of this memory is communicated to the Endpoint, which becomes the egress translation destination address. For egress source address, the address must fall within the PCIe address range as defined in System Addresses. This is 256 MB in the 4G address space and 8 GB and 256 GB for higher address widths. A typical flow is illustrated in This Figure.

Figure 30-11:      Egress Transfer Flow Chart

X-Ref Target - Figure 30-11

X18018-egress-flow.jpg