Enable Sequence

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.SWDT is reset by a power-on reset.

2.Disable the timer by clearing the WDEN bit. Write AB_C000h to the mode register. This disables the timer and sends the correct [ZKEY] bit field of 12'h0ABC. The other bits can be 0 for now.

3.Initialize the counter control register. For example, writing 0x0923C to the control register sets the divide by eight prescalar and the counter restart value to its maximum.The [CKEY] value in bits 25:14 must be 12'h0248.

4.Enable the timer. For example, writing 0xABC1C5 to the mode register. Bit 0, [WDEN] enables the timer. Bit 1, [RSTEN] deasserts reset. Bit 2, [IRQEN] enables interrupts. Always write 0 to bit 3. Also, IRQLN and RSTLN must be greater than or equal to the specified minimum values.