Endpoint Mode DMA Operation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section describes the DMA operation when the Zynq UltraScale+ MPSoC controller for PCIe is used as an Endpoint. The dual CPU mode is outlined, where a single DMA channel is managed by both source and sink processors. The AXI CPU and PCIe CPU can each become source or sink based on the direction of data transfer.

The DMA Operation section describes the dataflow for this mode. Once the core is configured for Endpoint mode of operation, the DMA activity can be divided into three phases.

Initialization Phase: initializes the DMA channel, sets up the descriptor elements.

DMA Phase: the DMA operation phase.

Exit Phase: the DMA transaction completes and the allocated resources are released in this phase.