Enhanced Configuration Access Mechanism

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The bridge implements ECAM to translate AXI read or write transactions to PCIe configuration read or write TLPs. ECAM maps a portion of the AXI memory address space to the PCI Express configuration transactions. A write transaction targeting this region is converted into a PCI Express configuration write transaction and a read transaction targeting this region is converted into a PCI Express configuration read transaction.

The ECAM region is hit when the following occurs.

ECAM is enabled (ecam_enable == 1).

The ecam_base[63:(12+ecam_size)] == AXI address[63:(12+ecam_size)].

On a hit, the lower AXI address bits are mapped into the PCI Express configuration transaction as listed in Table: AXI Address to PCIe Configuration TLP Mapping.

Table 30-3:      AXI Address to PCIe Configuration TLP Mapping

AXI Address Bits(1)

PCIe Configuration TLP Field

Notes

AXI address [27:20]

Bus number [7:0].

If ecam_size is set less than 256 MB, then the upper bus number bits that are not controlled by the AXI address are set to 0.

AXI address [19:12]

AXI address[19:15] = Device Number[4:0].

For PCI Express devices, implementing an alternative routing ID (ARI).

AXI Address[19:12] = Function Number[7:0].

AXI address [14:12]

Function number [2:0].

 

AXI address [11:2]

Configuration register DWORD
address [11:2].

 

Notes:

1.AXI address[1:0] along with AXI transaction size are used to compute the transaction byte enables.

ECAM transactions are not permitted to cross a DWORD address boundary. If a transaction hit to the ECAM region crosses a DWORD address boundary or times out, the transaction is aborted with SLVERR.

Note:   The bridge generates SLVERR for ECAM transactions when the link is down. Software is required to check for link up status before sending ECAM transactions. The exception to this is during access of the local root configuration space (bus number = 0) when the PCIe controller is used as the Root Port.