Entering Deep Power-down

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

By setting the PWRCTL.deeppowerdown_en bit, the SDRAM device can be put into deep power-down mode if all of these conditions are true:

The period specified by PWRTMG.powerdown_to_x32 has passed while the DDRC is idle (except for issuing refreshes).

PWRCTL.selfref_sw = 0.

PWRCTL.selfref_en = 0.

If HWLPCTL.hw_lp_en = 1, DPD is entered only when the hardware low power interface has completed a self-refresh exit. (This can be checked by observing STAT.operating_mode and STAT.selfref_type).

If HWLPCTL.hw_lp_exit_idle_en = 1, DPD is entered only when all bits of
cactive_in_ddrc = 0.

Entering deep power-down includes these steps:

1.If there is a self-refresh exit previously, wait for at least one refresh command (or eight per-bank refresh commands if LPDDR3 per-bank refresh is enabled) to all active ranks. Auto-refresh logic must be enabled, or refresh should be issued using direct software requests of refresh command via DBGCMD.rank*_refresh.

2.Precharging (closing) all open pages. Pages are closed one at a time in no specified order.

3.Waiting for tRP (row precharge) idle period.

4.Issuing the command to enter deep power-down. For multi-rank systems, all chip-selects are asserted so that all ranks enter deep power-down simultaneously. The deep power-down entry commands are CKE=0, CSN=0, CA0=1, CA1=1, and CA2=0.

5.This step occurs only if the DFI low power interface for deep power-down is enabled (DFILPCFG0.dfi_lp_en_dpd). It attempts an entry to low power mode via DFI low power interface with dfi_lp_wakeup set by DFILPCFG0.dfi_lp_wakeup_dpd. The low power entry attempt is delayed with DFITMG0.dfi_t_ctrl_delay + DRAMTMG6.t_ckdpde clock cycles, this is needed to satisfy SDRAM timings related to disabling clocks when the PHY is programmed to gate the clock, to save maximum power.

If the DDRC receives a read or write request from the SoC core during step 1 or step 3, the deep power-down entry is immediately aborted. The same is true if PWRCTL.deep_powerdown_en is driven to 0 during step 1 or step 3. Once the deep power-down entry command is issued, proper deep power-down exit is required, as described in the following section.

Note:   Contents of SDRAM might be lost upon entry into deep power-down mode.