Entering Maximum Power Saving Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

By setting the PWRCTL.mpsm_en bit, you can put the DDR4 devices into maximum power saving mode, if all of these conditions are true:

The DDRC is idle (except for issuing refreshes).

PWRCTL.selfref_sw = 0.

PWRCTL.selfref_en = 0.

If HWLPCTL.hw_lp_en = 1, MPSM is entered only when the hardware low power interface has completed a self-refresh exit. (This can be checked by observing STAT.operating_mode and STAT.selfref_type).

If HWLPCTL.hw_lp_exit_idle_en=1, MPSM is entered only when all bits of cactive_in_ddrc = 0.

If CA parity is enabled, the DDRC disables CA parity before entering maximum power saving mode, and enables the CA parity after exiting maximum power saving mode. Note that the DDRC uses the setting of INIT6.mr5[2:0] to determine whether to perform this disabling/enabling of CA parity, and uses the entire INIT6.mr5[15:0] for the automatic MRS commands. Consequently, if any part of the SDRAM’s MR5 is updated by software, it is also the responsibility of the software to update INIT6.mr5 so that it is aligned to the SDRAM’s MR5, if it is intended to enter MPSM.

If CAL mode is enabled, the DDRC disables CAL mode before entering maximum power saving mode, and enables CAL mode after exiting maximum power saving mode.

If geardown is enabled, the user must disable geardown by using self-refresh, before setting the PWRCTL.mpsm_en, as follows:

1.Put SDRAM in self-refresh mode by setting PWRCTL.selfref_sw to 1 and polling STAT.operating_mode.

2.Disable geardown mode by setting MSTR.geardown_mode to 0.

3.Wake SDRAM up from self-refresh by setting PWRCTL.selfref_sw to 0 and polling STAT.operating_mode (geardown is disabled).

The DDRC does not disable or enable geardown before entering or after exiting MPSM.

Entering maximum power saving mode includes the following steps:

1.If there is a self-refresh exit previously, wait for at least one refresh command to all active ranks. Auto-refresh logic must be enabled, or refresh should be issued using direct software requests of refresh command via DBGCMD.rank*_refresh.

2.Precharging (closing) all open pages. Pages are closed one-at-a-time (not in a specified order).

3.Waiting for tRP (row precharge) idle period.

4.Issuing the MRS command to enter maximum power saving mode. For multi-rank systems, MRS commands should be sent to all ranks. This occurs either simultaneously, to even and odd ranks separately, or to each rank separately, depending on the value of registers DIMMCTL.dimm_output_inv_en, DIMMCTL.dimm_addr_mirr_en, and DIMMCTL.dimm_stagger_cs_en.

5.This step occurs only if DFI low power interface for maximum power saving mode is enabled (DFILPCFG1.dfi_lp_en_mpsm). It attempts an entry to low power mode via DFI low power interface with dfi_lp_wakeup set by DFILPCFG1.dfi_lp_wakeup_mpsm. The low power entry attempt is delayed with DFITMG0.dfi_t_ctrl_delay + DRAMTMG11.t_ckmpe clock cycles, this is needed to satisfy SDRAM timings related to disabling clocks when the PHY is programmed to gate the clock, to save maximum power.

If the DDRC receives a read or write request from the SoC core during step 1 or step 2, the maximum power saving mode entry is immediately aborted. The same is true if PWRCTL.mpsm_en is driven to 0 during step 1 or step 2. Once the maximum power saving mode entry command is issued, proper maximum power saving mode exit is required as described in the next section.