The error correcting code (ECC) block consists of an encoder and a decoder that can detect and correct single-bit errors, and detect double-bit errors for configurations where the DRAM data width is configured to be 32 or 64 bits. The syndrome bits are calculated on a 32-bit or 64-bit basis based on DRAM data width selection. The ECC block support only covers the data bus and is not applicable for address and command bus. ECC is not supported for LPDDR3.
The ECC block has these features:
•Hamming code based ECC calculations
•Single-bit error detection and correction
•Double-bit error detection
•Error counter for single-bit and double-bit errors
•Supports error injection (single-bit and double-bit errors) for testing and debugging
•Interrupt generation on error
This Figure illustrates the interface between the DDR subsystem and DRAM memories with ECC enabled.
The ECC feature can be enabled or disabled by programming the ECCCFG0.ecc_mode register. If ECCCFG0 [ecc_mode] = 100, the ECC is enabled and the controller performs the following functions.
•On writes, the syndrome is calculated across DRAM data width, and the resulting ECC code is written as an additional byte along with the data as shown in This Figure. This additional ECC byte is always written to the uppermost byte (byte 8 for both 32-bit and 64-bit DRAM).
•On reads, the DRAM data bus including the ECC byte is read from the DRAM and is then decoded. A check is performed to verify that the ECC byte is as expected, based on the data in DRAM data bus. If it is correct, the data is sent to the processing system as normal. If it is not correct it executes steps as described in ECC Error Behavior.
•On read-modify-write operations, first a read is performed. The read data is then combined with the write data, making use of the write mask received to over-write certain bytes of the data that are read. The ECC is then calculated on the resulting data, and the write is performed.
Note: Avoid streaming high priority, non 64-bit write transactions to memory when ECC is enabled. The read-modify-write sequences negatively impact memory controller performance and might cause unrelated high throughput video traffic to be starved.
Note: Enabling ECC on the DDR can diminish overall available memory bandwidth or increase access latency under certain conditions. System designers should carefully consider the trade offs between enabling ECC and bandwidth/latency requirements of other components in the system, when there is a possibility of a significant amount of partial (sub-64 bit) writes to memory. See Answer Record 67651 for more information.